ucc1817/18 ucc2817/18 ucc3817/18 preliminary description the ucc1817/ucc1818 provides all the functions necessary for active power factor corrected preregulators. the controller achieves near unity power factor by shaping the ac input line current waveform to correspond to that of the ac input line voltage. average current mode control maintains stable, low distortion sinusoidal line current. designed in unitrode?s bicmos process, the ucc1817/ucc1818 offers new features such as lower start-up current, lower power dissipation, over-voltage protection, a shunt uvlo detect circuitry, a leading-edge mod - ulation technique to improve ripple current in the bulk capacitor and an im - proved, low-offset (2mv) current amplifier to reduce distortion at light load conditions. ucc1817 offers an on-chip shunt regulator with low start-up current, suit - able for applications utilizing a bootstrap supply. ucc1818 is intended for applications with a fixed supply (vcc). available in the 16-pin n, d, dw and j and 20 pin l and q packages. bicmos power factor preregulator features ? controls boost preregulator to near-unity power factor ? limits line distortion ? world wide line operation ? over-voltage protection ? accurate power limiting ? average current mode control ? improved noise immunity ? improved feed-forward line regulation ? leading edge modulation ? 150 a typical start-up current ? low power bicmos operation ? 12v to 17v operation 08/99 vref 9 2 16 1 15 10 5 4 drvout gnd cai vcc ovp/en vaout 1.5v pklmt 7.5v reference uvlo 16v/10v (ucc1817) 10.5v/10v (ucc1818) vcc 3 oscillator 12 rt 14 ct sq r pwm latch + ? pwm caout + ? + ? + ? ss voltage error amp 8.0v 13 7 11 vsense vff 8 iac 6 mout mirror 2:1 x 2 + ? 7.5v enable ovp x x mult osc clk clk current amp 16v (for ucc1817 only) + ? 0.25v + ? zero power block diagram udg-98182
2 ucc1817/18 ucc2817/18 ucc3817/18 soic-16, dil-16 (top view) d, dw, n and j packages absolute maximum ratings supply voltage vcc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18v gate drive current, continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2a 50%duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1a input voltage, cai, mout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8v pklmt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v vsense, ovp/en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10v input current, rt, iac, pklmt . . . . . . . . . . . . . . . . . . . . 10ma maximum negative voltage, drvout,pklmt,mout . . ?0.5v power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1w currents are positive into, negative out of the specified termi - nal. consult packaging section of databook for thermal limita - tions and considerations of packages. all voltages are referenced to gnd. drvout 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 vcc ct ss rt vsense ovp/en vref gnd pklmt caout cai mout iac vaout vff connection diagrams electrical characteristics: unless otherwise specified, these specifications hold for t a =0c to 70c for the ucc3817, ?40c to +85c for the ucc2817, and ?55c to +125c for the ucc1817, t a =t j . vcc = 12v, rt = 22k, ct = 330pf. parameter test conditions min typ max units supply current section supply current, off vcc = (vcc turnon threshold ? 0.3v) 150 300 a supply current, on vcc = 12v, no load on drvout 2 4 6 ma uvlo section vcc turn-on 15.4 16 16.6 v uvlo hysteresis 5.4 6 6.2 v maximum shunt voltage i vcc = 10ma 15.4 17 17.5 v vcc turn-on threshold (ucc1818) 10.2 10.5 10.8 v uvlo hysteresis (ucc1818) 0.4 0.5 0.6 v voltage amplifier section input voltage t a = 0c to 70c 7.387 7.5 7.613 v t a = ?40 c to +85 c 7.369 7.5 7.631 v t a = ?55 c to 125 c 7.313 7.5 7.687 v v sense bias current vsense = vref, vaout = 2.5v 50 200 na open loop gain vaout = 2v to 5v 90 db v out high i load = ?150 a 5.4 5.5 5.6 v v out low i load = 150 a 50 100 mv 3 18 17 16 1 22019 15 14 4 5 6 7 8 911 10 12 13 gnd pklmt drvout vcc ct ss n/c rt vsense caout cai n/c mout iac ovp/en vref n/c vaout vff gnd plcc-20, lcc-20 (top view) q, l packages ucc 81 ordering information
3 ucc1817/18 ucc2817/18 ucc3817/18 electrical characteristics: unless otherwise specified, these specifications hold for t a =0c to 70c for the ucc3817, ?40c to +85c for the ucc2817, and ?55c to +125c for the ucc1817, t a =t j . vcc = 12v, rt = 22k, ct = 330pf. parameter test conditions min typ max units over voltage protection and enable section over voltage reference 7.8 8 8.2 v hysteresis 500 mv enable threshold 1.0 1.5 2.0 v current amplifier section input offset voltage v cm = 0v, v caout = 3v ?2 0 2 mv input bias current v cm = 0v, v caout = 3v ?50 na input offset current v cm = 0v, v caout = 3v 25 na open loop gain v cm = 0v, v caout = 2v to 5v 90 db cmrr v cm = 0v to 1.5v, v caout = 3v 80 db v out high i load = ?120 a 6.3 v v out low i load = 1ma 0.2 v gain bandwidth product note 1 2.5 mhz voltage reference section input voltage ta = 0c to 70c 7.387 7.5 7.613 v ta = ?40c to +85c 7.369 7.5 7.631 v ta = ?55c to 125c 7.313 7.5 7.687 v load regulation i ref = 1ma to 2ma 3 mv line regulation vcc = 10.8v to 15v 20 mv short circuit current vref = 0v ?25 ma oscillator section initial accuracy t a = 25c 85 100 115 khz voltage stability vcc = 10.8v to 15v 1 % total variation line, temp 80 120 khz ramp peak voltage 4.5 5 5.5 v ramp amplitude voltage (peak to peak) 4 v peak current limit section pklmt reference voltage ?15 15 mv pklmt propogation delay 350 ns multiplier section high line, low power i ac = 500 a, v ff = 4.7v, vaout = 1.25v ?6 a high line, high power i ac = 500 a, v ff = 4.7v, vaout = 5v ?90 a low line, low power i ac = 150 a, v ff = 1.4v, vaout = 1.25v ?19 a low line, high power i ac = 150 a, v ff = 1.4v, vaout = 5v ?300 a iac limited i ac = 150 a, v ff = 1.3v, vaout = 5v ?300 a gain constant (k) i ac = 300 a, v ff = 3v, vaout = 2.5v 1 1/v zero current i ac = 150 a, v ff = 1.4v, vaout = 0.25v 0 ?2 a i ac = 500 a, v ff = 4.7v, vaout = 0.25v 0 ?2 a i ac = 500 a, v ff = 4.7v, vaout = 0.5v 0 ?3 a power limit i ac = 150 a, v ff = 1.4v, vaout = 5v ?420 w feed-forward section vff output current i ac = 300 a ?150 a soft start section ss charge current ?10 a
4 ucc1817/18 ucc2817/18 ucc3817/18 cai: (current amplifier non-inverting input) this input and the inverting input (mout) remain functional down to and below gnd. caout: (current amplifier output) this is the output of a wide bandwidth op amp that senses line current and commands the pfc pulse-width modulator (pwm) to force the correct current. ct: (oscillator timing capacitor) a capacitor from ct to gnd will set the pwm oscillator frequency according to: () f rt ct = ? ? ? ? ? ? ? 0 725 . the lead from the oscillator timing capacitor to gnd should be as short and direct as possible. drvout: (gate drive) the output drive for the pfc stage is a totem pole mosfet gate driver on drvout. use a series gate resistor of at least 5 ? to prevent interaction between the gate impedance and the drvout output driver that might cause the drvout to overshoot exces - sively. some overshoot of the drvout output is always expected when driving a capacitive load. gnd: (ground) all voltages measured with respect to ground. vcc and ref should be bypassed directly to gnd with a 0.1f or larger ceramic capacitor. iac: (input ac current) this input to the analog multiplier is a current. the multiplier is tailored for very low distor - tion from this current input (i ac ) to multiplier output. rec - ommended maximum i ac is 500 a. mout: (multiplier output and current amplifier inverting input) the output of the analog multiplier and the invert - ing input of the current amplifier are connected together at mout. as the multiplier output is a current, this is a high impedance input so the amplifier can be configured as a differential amplifier. this configuration improves noise immunity and allows for the leading-edge modula- tion operation. the multiplier output current is given by the equation: () i vaout i vk mult ac ff = ? ? ?1 2 ; where k = 1 (multiplier gain constant.) ovp/en: (over-voltage/enable) a window comparator in - put which will disable the output driver if the boost output is 5% above nominal or will disable both the pfc output driver and reset ss if pulled below 1.5v. pklmt: (pfc peak current limit) the threshold for peak limit is 0v. use a resistor divider from the negative side of the current sense resistor to vref to level shift this sig - nal to a voltage level defined by the value of the sense resistor and the peak current limit. peak current limit is reached when pklmt voltage falls below 0v. rt: (oscillator charging current) a resistor from rt to gnd is used to program oscillator charging current. a re - sistor between 10k ? and 100k ? is recommended. ss: (soft start) ss is at ground for either enable low or vcc too low conditions. when enabled, ss will charge an external capacitor with a current source. this voltage will be used as the voltage error signal during start-up, enabling the pwm duty cycle to increase slowly. in the event of a disable command or a vcc dropout, ss will quickly discharge to disable the pwm. pin descriptions electrical characteristics: unless otherwise specified, these specifications hold for t a =0c to 70c for the ucc3817, ?40c to +85c for the ucc2817, and ?55c to +125c for the ucc1817, t a =t j . vcc = 12v, rt = 22k, ct = 330pf. parameter test conditions min typ max units gate driver section pull up resistance i out = ?100ma 7 pull down resistance i out = 100ma 3 output rise time c load = 1nf, r load = 10 25 ns output fall time c load = 1nf, r load = 10 10 ns zero power section zero power comparator threshold measured on vaout 0.10 0.25 0.40 v note 1: guaranteed by design, not 100% tested in production.
5 ucc1817/18 ucc2817/18 ucc3817/18 vaout: (voltage amplifier output) this is the output of the opamp that regulates output voltage. the voltage am - plifier output is internally limited to approximately 5.5v to prevent overshoot. vcc: (positive supply voltage) connect to a stable source of at least 20ma between 10v and 17v for nor - mal operation. bypass vcc directly to gnd to absorb supply current spikes required to charge external mosfet gate capacitances. to prevent inadequate gate drive signals, the output devices will be inhibited unless vcc exceeds the upper under-voltage lockout voltage threshold and remains above the lower threshold. vff: (feed-forward signal) rms signal generated at this pin by mirroring i ac into a single pole external filter. r vff iac vff max max = ?? 2 2 09 . vsense: (voltage amplifier inverting input) this is nor - mally connected to a compensation network and to the boost converter output through a divider network. vref: (voltage reference output) vref is the output of an accurate 7.5v voltage reference. this output is capa - ble of delivering 10ma to peripheral circuitry and is inter - nally short circuit current limited. vref is disabled and will remain at 0v when v cc is below the uvlo threshold. bypass vref to gnd with a 0.1f or larger ceramic ca - pacitor for best stability. pin descriptions (cont.) the ucc3817 is a bicmos average current mode boost controller for high power factor, high efficiency preregulator power supplies. fig. 1 shows the ucc3817 in a 250w pfc preregulator circuit. off-line switching power converters normally have an input current that is not sinusoidal. the input current waveform will have high harmonic content because current is drawn in pulses at the peaks of the input voltage waveform. an active power factor correction circuit programs the input current to fol- low the line voltage, forcing the converter to look like a resistive load to the line. a resistive load has 0 phase displacement between the current and voltage wave - forms. power factor can be defined in terms of the phase angle between two sinusoidal waveforms of the same frequency: pf = cos therefore, a purely resistive load would have a power factor of 1. in practice, power factors of 0.999 with thd (total harmonic distortion) less than 3% are possible with a well-designed circuit. following guidelines are provided to design pfc boost converters using the ucc3817. power stage l boost : the boost inductor value is determined by: () () () l vd if boost in s = ? ? min ? where d is the duty cycle, ? i is the inductor ripple cur - rent and f s is the switching frequency. for the example circuit a switching frequency of 100khz, a ripple current of 875ma, a maximum duty cycle of 0.688 and a mini - mum input voltage of 85v rms gives us a boost inductor value of about 1mh. the values used in this equation are at the peak of low line, where the inductor current and its ripple are at a maximum. c out : two main criteria, the capacitance and the voltage rating, dictate the selection of the output capacitor. the value of capacitance is determined by the hold-up time required for supporting the load after input ac voltage is removed. hold-up is the amount of time that the output stays in regulation after the input has been removed. for this circuit, the desired hold-up time is approximately 16ms. expressing the capacitor value in terms of output power, output voltage, and hold-up time gives the equa - tion: () () () c pt vv out out out out = ?? 2 22 ? ? min in practice the calculated minimum capacitor value may be inadequate because output ripple voltage specifica - tions limit the amount of allowable output capacitor esr. attaining a sufficiently low value of esr often necessi - tates the use of a much larger capacitor value than cal - culated. the amount of output capacitor esr allowed can be determined by dividing the maximum specified output ripple voltage by the inductor ripple current. in this design hold-up time was the dominant determining factor and a 220 f, 450v capacitor was chosen for the output voltage level of 385vdc at 250w. power switch selection as in any power supply design, tradeoffs between perfor - mance, cost and size have to be made. when selecting a power switch it can be useful to calculate the total power application information
6 ucc1817/18 ucc2817/18 ucc3817/18 1 11 7 16 gnd drvout r17 20 ? 15 c3 1 fcer vcc c2 100 faiei 14 c1 720pf 13 c4 0.01 f 12 r1 10k r3 19.9k r2 1m r4 500k r5 10k c5 1 f 9 4 10 v ref vcc ct ss rt vsense ovp/en vref vaout 3 8 2 vff c6 2 f c7 150nf r7 98k 6 5 r9 4k c8 260pf r8 12k d6 (optional) r10 4k d5 (optional) r11 10k r12 1.6k r14 0.25 ? 5w c13 0.47 f 600v c14 1.5 f 400v r13 760k iac r15b 240k r15a 240k r16 100 ? vcc c10 1 f c11 1 f d7 d8 l1 1mh d2 6a, 600v d1 8a, 600v c12 220 f 450v v out 385v dc + ? pklimit caout cai mout iac v out ucc3817 v line 85-270 v ac v ref c9 1.3nf r6 30k 6a 600v d3 f1 application information (cont.) figure 1. typical application circuit. udg-98183 dissipation in the switch for several different devices at the switching frequencies being considered for the con - verter. total power dissipation in the switch is the sum of switching loss and conduction loss. switching losses are the combination of the gate charge loss, c oss loss and turn-on and turn-off losses: pqvfs pcvfs pp gate gate gate coss oss off on off =?? =? ? ? + 1 2 2 () =? ? ? + ? 1 2 vitt f off l on off s where q gate is the total gate charge, v gate is the gate drive voltage, f s is the clock frequency, c oss is the drain source capacitance of the mosfet, t on and t off are the switching times (estimated using device parameters r gate ,q gd and v th ) and v off is the voltage across the switch during the off time, in this case v off =v out . conduction loss is calculated as the product of the r ds(on) of the switch (at the worst case junction tempera - ture) and the square of rms current: () pr ki cond ds on rms =?? 2
7 ucc1817/18 ucc2817/18 ucc3817/18 where k is the temperature factor found in the manufac - turer?s r ds(on) vs. junction temperature curves. calculating these losses and plotting against frequency gives a curve which enables the designer to determine either which manufacturer?s device has the best perfor - mance at the desired switching frequency, or which switching frequency has the least total loss for a particu - lar power switch. in this example the switch was chosen as the best trade off between performance, availability and cost. an excellent review of this procedure can be found in the unitrode power supply design seminar sem1200, topic 6, design review: 140w, [ multiple out - put high density dc/dc converter ]. multiplier the output of the multiplier of the ucc3817 is a signal representing the desired input line current. it is an input to the current amplifier, which programs the current loop to control the input current to give high power factor oper - ation. as such, the proper functioning of the multiplier is key to the success of the design. the inputs to the multi- plier are vaout, the voltage amplifier error signal, iac, a representation of the input rectified ac line voltage, and an input voltage feedforward signal, v ff . the output of the multiplier, i mo , can be expressed: () i i vaout kv mo ac ff = ? ? ?1 2 where k is a constant typically equal to 1. the i ac signal is obtained through a high value resistor connected between the rectified ac line and the iac pin of the ucc3817. this resistor is sized to give the maxi - mum i ac current at high line. for this device the maxi - mum i ac current is about 500 a. a higher current than this can drive the multiplier out of its linear range. a smaller current level will be functional, but noise can be - come an issue, especially at low input line. assuming a universal line operation of 85 to 265vac gives a resistor value of 750k ? . because of voltage rating constraints of standard 1/4w resistors, use a combination of lower value resistors connected in series to give the 750k ? value and distribute the high voltage across two or more resistors. the current through the i ac resistor is mirrored internally to the vff pin where it is filtered to produce a voltage feedforward signal proportional to line voltage and free of a 120hz ripple component. this second harmonic ripple component at the vff pin is one of the major contribu - tors to harmonic distortion in the system, so adequate fil - tering is crucial. refer to unitrode power supply design seminar, sem-700 topic 7, [ optimizing the design of a high power factor preregulator. ] assuming that an allo - cation of 1.5% total harmonic distortion from this input is allowed, and that the second harmonic ripple is 66% of the input ac line voltage, the amount of attenuation re - quired by this filter is: 15 66 022 .% % . or a ripple frequency (f r )of 120hz and an attenuation of .022 gives us a single pole filter with: fp hz hz =?= 120 0 022 2 6 .. the range of this input to the multiplier should be 0.5v to 5.5v over the line input range. therefore the filter resistor should be sized accordingly. maximum i ac current is 500 a, mirrored 2:1 to vff becomes 250 a. the dc output is 90% of the rms value of this half sine wave, or 159 a. so the filter resistor should be equal to the volt - age swing of the input to the multiplier divided by the dc current or: 5 159 31 44 v a k = . ? select 30k ? for a standard value. solving for the capaci- tor value: () () c khz f f == 1 230 26 2 . this results in a single pole filter, which will adequately attenuate the harmonic distortion and also meet the dc requirement of the proper voltage swing across line con - ditions. the r mo resistor is sized to match the maximum current through the sense resistor to the maximum multiplier cur - rent. the maximum multiplier current, or i mo(max) , can be determined by the equation: () () () i iv v v kv mo ac in ea ff max (min) (max) min @? = ? ? 1 2 i mo(max) for this design is approximately 315 a. the r mo resistor can then be determined by () r v i mo rs mo = max in this example r mo is equal to 3.91k ? . voltage loop the second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic of the line frequency. this ripple is fed back through the er - ror amplifier and appears as a 3rd harmonic ripple at the application information (cont.)
8 ucc1817/18 ucc2817/18 ucc3817/18 input to the multiplier. the voltage loop must be compen - sated not just for stability but also to attenuate the contri - bution of this ripple to the total harmonic distortion of the system. refer to fig. 2. the gain of the voltage amplifier, g va , can be deter - mined by first calculating the amount of ripple present on the output capacitor. the peak value of the second har - monic voltage is given by the equation: () v p fc v opk in routout = ?? ? 2 in this example v opk is equal to 3.91v. assuming an al - lowable contribution of 0.75% (1.5% peak to peak) from the voltage loop to the total harmonic distortion budget we set the gain equal to: () g v v va aout opk = ? ? 15 .% where v aout is the effective output voltage range of the error amplifier (5.5v for the ucc3817). the network needed to realize this filter is comprised of an input resis - tor, r in , and feedback components c f and r f . the value of r in is already determined because of its function as one half of a resistor divider from v out feeding back to the voltage amplifier for output voltage regulation. in this case the value was chosen to be 1m ? . this high value was chosen to reduce power dissipation in the resistor. in practice, the resistor value would be realized by the use of two 500k ? resistors in series because of the voltage rating constraints of most standard 1/4w resistors. the value of c f is determined by the equation: () c fg r f rvain = ?? ? 1 2 in this example c f equals 65nf. resistor r f sets the dc gain of the error amplifier and thus determines the fre - quency of the pole of the error amplifier. the location of the pole can be found by setting the gain of the loop equation to one and solving for the crossover frequency. the frequency, expressed in terms of input power, can be calculated by the equation: () f p vvrcc vi in aout out in out f 2 2 = ????? ? f vi for this converter is 15hz. a derivation of this equation can be found in the unitrode power supply design semi - nar sem1000, topic 1, [ a 250khz, 500w power factor correction circuit employing zero voltage transitions ]. solving for r f becomes: () r fc f vi f = ?? 1 2 or r f equals 150k ? . current loop the gain of the power stage is: () () () gs vr sl v id out sense boost p = ? ?? r sense has been chosen to give the desired differential voltage for the current sense amp at the desired current limit point. in this example a current limit of 4a and a rea - sonable differential voltage to the current amp of 1v gives a r sense value of 0.25 ? .v p in this equation is the voltage swing of the oscillator ramp, 4v for the ucc3817. setting the crossover frequency of the system to 1/10th of the switching frequency, or 10khz, requires a power stage gain at that frequency of 0.383. in order for the system to have a gain of 1 at the crossover frequency, the current amplifier needs to have a gain of 1/g ps at that frequency. g ea , the current amp gain is then: g g ea id == = 11 0 383 2 611 . . refer to fig. 3. r i is the r mo resistor, previously calcu - lated to be 3.9k ? . the gain of the current amp is r f /r i ,so multiplying r i by g ea gives the value of r f , in this case approximately 10k ? . setting a zero at the crossover fre - quency and a pole at half the switching frequency com - pletes the current loop compensation. c rf z fc = ?? ? 1 2 c r p f fs = ?? ? 1 2 2 application information (cont.) r in r d r f c f v ref v out figure 2. voltage amplifier configuration.
9 ucc1817/18 ucc2817/18 ucc3817/18 the ucc3817 current amplifier has the input from the multiplier applied to the inverting input. this change in ar - chitecture from previous unitrode pfc controllers im - proves noise immunity in the current amplifier. it also adds a phase inversion into the control loop. the ucc3817 takes advantage of this phase inversion to im - plement leading-edge duty cycle modulation. synchro - nizing a boost pfc controller to a downstream dc to dc controller reduces the ripple current seen by the bulk ca - pacitor between stages, reducing capacitor size and cost and reducing emi. this is explained in greater detail in a following section. the ucc3817 current amplifier config - uration is shown in fig. 4. start up current the ucc3818 version of the device is intended to have vcc connected to a 12v supply voltage. the ucc3817 has an internal shunt regulator enabling the device to be powered from bootstrap circuitry as shown in the typical application circuit of fig. 1. the current drawn by the ucc3817 during under-voltage lockout, or start up cur- rent, is typically 150 a. once vcc is above the uvlo threshold, the device is enabled and will draw 4ma typi- cally. a resistor connected between the rectified ac line voltage and the vcc pin provides current to the shunt regulator during power-up. once the circuit is operational the bootstrap winding of the inductor will provide the vcc voltage. sizing of the start-up resistor is determined by the start-up time requirement of the system design. ic v t r v i startup rms startup =? = ? ? where i is the start-up current, c is the total capacitance at the vcc pin, v is the uvlo threshold and t is the al - lowed startup time. assuming a 1 second allowed start-up time, a 16v uvlo threshold, and a total vcc capacitance of 100 f, a resis - tor value of 75k ? is required at a low line input voltage of 80v rms . the ic start-up current is sufficiently small as to be ignored in sizing the start up resistor. leading edge modulation the ucc3817 uses leading edge modulation as op - posed to traditional trailing edge modulation. leading edge modulation in a boost pfc front end synchronized to a downstream buck converter using trailing edge mod - ulation greatly diminishes the ripple current in the boost bulk capacitor. refer to fig. 5. in a conventional synchronized system with both regula - tors utilizing trailing edge modulation, q1 and q2 would be turned on at the same time. all of the charging current for l1 would go to ground through q1 and all of the out- put current would come from the bulk capacitor through q2. similarly, when both fets are turned off, all the in- ductor current will flow into the bulk capacitor and all of the output current will be supplied by the freewheeling di- ode d2. by using leading edge modulation on the boost converter the fets are turned on and off alternately. re- fer to fig. 6. when q1 is off and q2 is on, some of the output current is supplied through diode d1 by the boost inductor l1. when q1 is on and q2 off, the charge on the bulk capacitor is held up by the blocking action of q2. it can be seen that the rms current through the bulk ca - pacitor is minimized when t1 and t3 are maximized with respect to t2 and t4. this greatly reduces the ripple cur - rent seen by the bulk capacitor, reducing stress and in - creasing reliability. application information (cont.) r sense + ? mult z f pwm comparator ca q boost l boost v out figure 4. ucc3817 current amplifier configuration. r i r f c p caout c z figure 3. current loop compensation.
10 ucc1817/18 ucc2817/18 ucc3817/18 t1 t2 t3 t4 t s i d1 i q2 i c i ac -i l i ac 0?i l i l i ac t s q2 q1 figure 6. timing relationships show capacitor current cancellation. application information (cont.) unitrode corporation 7 continental blvd. merrimack, nh 03054 tel. (603) 424-2410 fax (603) 424-3460 q2 d2 c bulk q1 l1 buck derived converter pfc boost circuit d1 i ac i q1 i c i q2 i d1 i l figure 5. leading edge modulation. udg-98186
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